1. Field of the Invention
The present invention relates to a sense amplifier for sensing and amplifying a memory cell data potential, and more particularly relates to a differential sense amplifier formed of insulated gate type field effect transistors in a dynamic random access memory.
2. Description of the Related Art
A personal computer and a work station generally contain a memory for data storage. There is a DRAM (Dynamic Random Access Memory) having a large storage capacity and having data readable and writable as such a memory, which is used as a main memory in a personal computer, a work station and such.
FIG. 1 shows a configuration of a sense amplifier and peripheral circuitry thereof in a conventional DRAM, as disclosed in Japanese Patent Laying-Open No. 2-231760, for example.
Referring to FIG. 1, a sense amplifier 5 receives as power source potentials an operational power supply potential Vcc at a power supply node 1a and a ground potential Vss at a ground node 1b, and senses and amplifies the difference of potentials on bit lines 2a and 2b in response to sense amplifier enable signals SEN and SEP.
Sense amplifier 5 includes a p channel MOS (insulated gate type field effect) transistor 5a connected between power supply node 1a and a node 5b and receiving the sense amplifier enable signal SEP at a gate thereof, and a PMOS sense amplifier 5c for bringing a potential of a bit line having a higher potential out of bit lines 2a and 2b to power supply potential Vcc, an n channel MOS transistor 5f connected between ground node 1b and a node 5e and receiving the sense amplifier enable signal SEN, and an n MOS sense amplifier 5d for bringing a potential of a bit line at a lower potential out of bit lines 2a and 2b to ground potential Vss.
PMOS sense amplifier 5c includes a p channel MOS transistor 5ca connected between node 5b and bit line 2a and having a gate connected to bit line 2b, and a p channel MOS transistor 5cb connected between node 5b and bit line 2b and having a gate connected to bit line 2a.
NMOS sense amplifier 5d includes an n channel MOS transistor 5da connected between a node 5e and bit line 2a and having a gate connected to bit line 2b, and an n channel MOS transistor 5db connected between node 5e and bit line 2b and having a gate connected to bit line 2a. NMOS transistors 5da and 5db are formed in a well region which is isolated from any other circuit regions and is supplied with a well potential VSB from a well potential control circuit 6.
Well potential control circuit 6 includes a current mirror type differential amplifier 6a responsive to a control signal /.phi.STR for amplifying the difference between a reference voltage Vref and a potential Va at node 5e for outputting a signal indicating the result of amplification, and a control circuit 6b responsive to a control signal .phi.STR and the signal from the amplifier 6a for producing the well potential VSB.
Differential amplifier includes a p channel MOS transistor 6aa connected between power supply node 1a and a node 6ab and receiving the control signal /.phi.STR at a gate thereof, a p channel MOS transistor 6ac connected between node 6ab and a node 6ad and having a gate connected to node 6ad, a p channel MOS transistor 6af connected between node 6ab and a node 6ag and having a gate connected to node 6ag, an n channel MOS transistor 6ae connected between node 6ad and ground node 1b and receiving the reference potential Vref, and an n channel MOS transistor 6ah connected between node 6ag and ground node 1b and having a gate receiving the potential at node 5e.
Transistors 6ac and 6af constitute a current mirror circuit to supply a current to respective transistors 6ae and 6ab, which in turn constitute a comparison stage.
Control circuit 6b includes an n channel MOS transistor 6ba connected between a node receiving an intermediate potential Vcc/2 and a node 6bc and having a gate receiving the control signal .phi.STR, a p channel MOS transistor 6bd connected between node 6bc and ground node 1b and having a gate receiving the output signal at node 6ag of the amplifier 6a, and a capacitor 6be connected between node 6bc and ground node 1b. Well potential VSB is generated at node 6bc.
Control signal .phi.STR is made high until sense amplifier enable signal SEN is made active (high) when a memory cycle is started. Control signal /.phi.STR is made low until sense amplifier enable signal SEP is made active (low) when a memory cycle is started.
Word lines 3a and 3b are arranged crossing the bit lines 2a and 2b, respectively. Each of word lines 3a and 3b connects memory cells on a row, and each of bit lines 2a and 2b connects memory cells on a column (in an "open bit line arrangement").
Although memory cells are arranged in a matrix of rows and columns, two memory cells 4a and 4b are representatively shown in FIG. 1. Memory cell 4a is located at a crossing of word line 3b and bit line 2a, and includes a capacitor 4aa for storing information in a form of electric charges, and an n channel MOS transistor 4ab responsive to a potential on word line WLO for coupling the capacitor 4ab to bit line 2a. Capacitor 4aa receives a precharge potential Vp at intermediate potential Vcc/2 at one electrode (cell plate), and MOS transistor 4ab receives a predetermined, constant negative backgate bias potential VBB at a bulk (backgate).
Memory cell 4b similarly includes a capacitor 4ba and an n channel MOS transistor 4bb. Precharge potential Vp is also applied to cell plate of capacitor 4aa, and backgate bias potential VBB is applied to backgate of MOS transistor 4bb. The backgate bias potential VBB is also applied to a backgate of MOS transistor 5f in sense amplifier 6.
Now, operation of the circuitry shown in FIG. 1 will be described with reference to a waveform diagram of FIG. 2 representing an operation when an "L" level data stored in memory cell 4a is read out.
Before time t0 when a row address strobe signal RAS defining a memory cycle rises to an H (high) level, as shown at (a) in FIG. 2, sense amplifier enable signals SEP and SEN as shown respectively at (b) and (c) in FIG. 2 are H level and L level, respectively. P channel MOS transistor 5a and n channel MOS transistor 5f receiving the respective enable signals SEP and SEN at their gates are both non-conductive, and therefore power supply potential Vcc and ground potential Vss are not supplied to PMOS sense amplifier 5c and NMOS sense amplifier 5d, so that sense amplifier 5 is kept inactive.
Potentials WLO and WL1 on word lines 3a and 3b shown at (e) and (f) in FIG. 2 are both at L level, and MOS transistors 4ab and 4bb in memory cells 4a and 4b are both kept non-conductive, and data are held in memory cells 4a and 4b.
Potentials BL and/BL on bit lines 2a and 2b as shown at (g) in FIG. 2 are precharged at a precharge potential of Vcc/2 by not shown bit line precharge circuit. Potential Va at node 5e as shown at (i) in FIG. 2 is set at the bit line precharge potential by not shown precharge circuit, and MOS transistors 5da and 4db are both turned off.
Control signals /.phi.STR and .phi.STR are at H level and L level, respectively in accordance with row address strobe signal RAS and sense amplifier enable signals SEP and SEN, as shown at (d) in FIG. 2. P channel MOS transistor 6aa receiving the control signal /.phi.STR at the gate thereof is in a non-conductive state, and the differential amplifier 6a is held in the inactive state because power supply potential Vcc is not supplied to the amplifier. N channel MOS transistor 6ba receiving the control signal .phi.STR at the gate thereof is also in the non-conductive state, so that the control circuit 6b is kept inactive and well potential VSB generated at node 6bc is kept at ground potential Vss attained in the previous active cycle as shown at (b) in FIG. 2.
When row address strobe signal RAS rises to H level at time t0 as shown at (a) in FIG. 2, a standby cycle is completed and a memory cycle (active cycle) is started. Responsively, control signals /.phi.STR and .phi.STR go low and high, respectively, as shown at (d) in FIG. 2, to activate differential amplifier 6a and control circuit 6b in well potential control circuit 6.
Potential Va at node 5e in sense amplifier 5 is higher than reference potential Vref at this time, and the conductance of MOS transistor 6ah is greater than that of MOS transistor 6ae, so that node 6ag is discharged through MOS transistor 6ah to a potential at ground node 1b and the signal potential at node 6ag is made low to turn off MOS transistor 6bd in control circuit 6b. MOS transistor 6ba is turned on in response to the rise of control signal .phi.STR to charge the node 6bc at intermediate potential Vcc/2. Thus, well potential VSB generated from node 6bc rises at a predetermined time constant to Vcc/2, as shown at (b) in FIG. 2.
A row address signal incorporated at a rising edge of row address strobe signal RAS is decoded by not shown row decoder. Potential WL0 of word line 3a designated by the row address signal rises to H level at time t1, as shown at (e) in FIG. 2. Responsively, MOS transistor 4ab in memory cell 4a is made conductive to couple bit line 2a precharged at Vcc/2 with the electrode (storage node) at ground potential of capacitor 4aa. Electric charges on bit line 2a flow into the storage node of capacitor 4aa, and potential BL of bit line 2a is lowered a little from precharge potential Vcc/2, as shown at (g) in FIG. 2. Because potential WL1 of word line 3b is kept at L level, no data is read from memory cell 4b onto bit line 2b, and potential /BL of bit line 2b is maintained at precharge potential Vcc/2, as shown at (g) in FIG. 2.
When sense amplifier enable signal SEN is raised to H level at time t2 as shown at (c) in FIG. 2, MOS transistor 5f in sense amplifier 5 is made conductive to activate NMOS sense amplifier 5d, and potential BL of bit line 2a is fallen to ground potential Vss, as shown at (g) in FIG. 2. Potential Va at node 5e is also lowered down to ground potential Vss, and becomes lower than reference potential Vref. Thus, the signal generated from the differential amplifier 6a goes high to turn on MOS transistor 6bd. Since MOS transistor 6ba is turned off in response to control signal .phi.STR when sense amplifier enable signal SEN is made active, well potential VSB is brought to ground potential Vss through MOS transistor 6bd. Although control signal .phi.STR is made low when sense amplifier enable signal SEN is made high at time t2 as shown at (d) in FIG. 2, control signal /.phi.STR is still kept active at L level. The potential at node 6ag is proportional to the difference of potentials Vref and Va, and MOS transistor 6bd discharges node 6bc such that well potential VSb is lowered tracing the lowering of potential Va.
When sense amplifier enable signal SEP is made active at time t3 as shown at (b) in FIG. 2, control signal /.phi.STR is rendered inactive (high) as shown at (d) in FIG. 2 to deactivate the differential amplifier 6a. MOS transistor 5a turns on in response to the fall (activation) of sense amplifier enable signal SEP to activate PMOS sense amplifier 5c. Potential /BL on bit line 5c is pulled up to power supply potential Vcc as shown at (g) in FIG. 2. Sensing and amplifying operation of sense amplifier 5 completes when the small potential difference between bit lines 2a and 2b is amplified up to the potential difference between power supply potential Vcc and ground potential Vss.
Now, operational effect of controlling the well potential VSB will be described with reference to FIGS. 3A to 3C depicting the potentials of respective nodes of MOS transistors 5da and 5db in NMOS sense amplifier 5d shown in FIG. 1.
It is well known in the art that MOS transistor has a backgate effect wherein a threshold voltage changes depending on a backgate bias potential with respect to a source potential. A threshold voltage Vthn and a backgate bias potential VBB with respect to a source potential satisfy the following relationship: ##EQU1## where A and B each are a constant determined by transistor parameters. If .vertline.VBB.vertline. increases, Vthn also increases. Referring to FIG. 3A, in a standby state, MOS transistors 5da and 5db receive well potential VSB at 0 V (=Vss) at their gates and potential Va at Vcc/2 at their sources, where it is assumed that intermediate potential Vcc/2 is greater than the threshold voltage Vthn of MOS transistors 5da and 5db. In this condition, .vertline.VBB.vertline.=.vertline.Vcc/2.vertline., and MOS transistors 5da and 5db each have relatively large threshold voltage. Bit lines 2a and 2b are precharged to intermediate potential Vcc/2.
Referring to FIG. 3B, when a word line (30) is selected and driven to a selected state (high level potential), memory cell data is read out onto bit line 2a, the potential of bit line 2a changes from intermediate potential Vcc/2 to Vcc/2-.DELTA.V where .DELTA.V denotes a read out voltage, and the potential of bit line 2b maintains the precharge potential at intermediate potential Vcc/2. Potential Va at node 5e also maintains the precharge potential at intermediate potential Vcc/2. Well potential VSB changes from ground potential Vss (=0 V) to intermediate potential Vcc/2.
Before the start of sensing, well potential VSB is at intermediate potential Vcc/2. Thus, MOS transistors 5da and 5db each have the source and backgate potentials equal with each other, or .vertline.VBB.vertline.=0, and the threshold voltage of MOS transistors 5da and 5db becomes relatively small.
Referring to FIG. 3C, when sensing operation is started, potential Va at node 5a is lowered to ground potential Vss (=0 V). When the potential difference between bit line 2b and node 5e, or Vcc/2-Va becomes greater than the threshold voltage Vth of MOS transistor 5da, MOS transistor 5da turns on to discharge the bit line 2a. The threshold voltage Vth is smaller than that in the case of VSB=0 V, and bit line discharging can be caused soon after sense amplifier enable signal SEN is made active. That is, sensing operation is done at a higher speed as compared to the case where a constant well potential is applied.
During the lowering of potential Va at node 5e, well potential VSB is lowered following the lowering of potential Va, and the difference between potentials VSB and Va is kept substantially constant, and the threshold voltage Vth is accordingly kept constant at a small value.
Since the threshold voltage Vth is forcedly made small upon sensing operation, even if power supply voltage Vcc is reduced and the difference between the power supply voltage Vcc and the threshold voltage Vth with VSB at 0 V is very small, the threshold voltage Vth can be effectively made small and MOS transistors 5da or 5db can be reliably made conductive. Thus, a sense amplifier operates at a high speed even under a low power supply voltage condition.
However, while the minimum threshold voltage can be provided when the backgate potential (well potential) and the source potential (node 5e potential) are made equal, such countermeasure only eliminates the backgate effect. In general, MOS transistor has a threshold voltage of about 0.7-1.0 V with no backgate bias effect. On the other hand, according to the recent trend, power supply voltage is made lower and lower, or 3.3 V, 1.5 V or 1.2 V for the purpose of fast operation and of the reduction of power dissipation. If power supply voltage of 1.2 V is employed, intermediate potential Vcc/2 is 0.6 V, and MOS transistor of threshold voltage 0.7 V with no backgate effect cannot be used. That is, the conventional sense amplifier arrangement cannot be applied to a device operating with a low power supply potential.
In addition, as shown in FIG. 3C, MOS transistor 5db receives ground potential at its gate to be turned off after the sensing operation is completed. However, in this state, memory cell data is latched and the potential on bit line 2b is power supply potential. The threshold voltage Vth of MOS transistor 5db is kept small, and therefore a large subthreshold current flows from bit line 2b to ground node 1b (FIG. 1) through MOS transistor 5db and sense amplifier activating MOS transistor 5f (FIG. 1), and current consumption is increased. Here, a subthreshold current is a current flowing through MOS transistor when potentials at a gate and a source of the MOS transistor are equal to each other, and it is known in the art that the subthreshold current increases as the absolute value of the threshold voltage decreases.